The present invention relates to a method and apparatus for simply and easily generating a planarizing pattern which is used to planarize multilevel wiring layers formed in a semiconductor integrated circuit device, such as an LSI, and to a semiconductor integrated circuit device manufactured by using the method of generating a planarizing pattern.
To achieve higher-degree integration in an ultralarge-scale integrated circuit, recent interconnections have been implemented in multilevel wiring layers.
In the multilevel wiring layers, however, undulations of a wiring pattern formed in a lower-level layer exert an influence on an interlayer insulating film formed over the lower-level layer, so that undulations are also produced on the interlayer insulating film. The undulations of the interlayer insulating film cause a step coverage failure (an exposure failure during pattern transfer using a mask owing to a level difference equal to or larger than the depth of focus produced on a wafer), resulting in a broken wire and a defective wire in the wiring layer. Planarization of the surface of the interlayer insulating film is therefore essential technology for implementing a reliable multilayer wiring structure.
As typical technology for planarizing the interlayer insulating film, a resin coating method or the like has been used conventionally. However, the method is disadvantageous in that a sufficient degree of planarity cannot be achieved thereby. To eliminate the disadvantage, there has been proposed a method of planarizing the interlayer insulating film whereby a planarizing pattern (auxiliary pattern) is generated by using a CVD technique to be filled in the gap between adjacent wires.
As the method of generating a planarizing pattern using a CVD technique, there has been known one disclosed in Japanese Laid-Open Patent Publication HEI 5-267460.
A description will be given to the conventional method of generating a planarizing pattern with reference to the drawings. FIGS. 41(a) to 41(d) and FIGS. 42(a) and 42(b) illustrate the process of generating a planarizing pattern in the vicinity of a wiring pattern for propagating an LSI signal in accordance with the conventional method of generating a planarizing pattern.
First, a wiring pattern 1 shown in FIG. 41(a) is inverted to generate a wiring pattern 2 shown in FIG. 41(b), followed by a graphic reducing process of reducing the inverted wiring pattern 2 to generate a reduced inverted wiring pattern 3 as shown in FIG. 41(c). In this case, the inverted wiring pattern 2 is reduced by an amount corresponding to the minimum spacing between the adjacent wiring patterns I on the surface of a chip shown in FIG. 41(a).
Next, a dummy original pattern 5 as shown in FIG. 41(d) is generated. The dummy original pattern 5 is a geometric pattern composed of an array of identical simple geometric figures. Then, figure logical-MINUS operation (subtraction) is performed between the reduced inverted wiring pattern 3 and the dummy original pattern 5 to generate a planarizing pattern 6 as shown in FIG. 42(a). Thereafter, figure logical-OR operation is performed between the wiring pattern 1 and the planarizing pattern 6 to generate a final pattern as shown in FIG. 42(b).
In accordance with the foregoing method of generating a planarizing pattern, however, the planarizing pattern 6 generated in the vicinity of the wiring pattern 1 does not necessarily maintain the initial configuration of the dummy original pattern 5 because of a positional relationship between the wiring pattern 1 and the dummy original pattern 5. There may be cases where extremely small planarizing patterns 6a much smaller in size than the dummy original pattern 5 are generated, leading to the problem that some of the extremely small planarizing patterns 6a are smaller than layout design rules for the wiring pattern 1.
On the other hand, the number of the geometric figures composing the resulting planarizing pattern 6 is excessively increased, leading to the problem of an increased amount of data on the planarizing pattern 6.